1. Field of the Invention:
This invention relates to a semiconductor memory device, and more particularly to a DRAM having a trench-type capacitor configuration wherein memory cells are constituted by MOSFETs and trench MOS capacitors.
2. Description of the Prior Art:
In recent years, considerable progress has been made in semiconductor technology, particularly in achieving high-density integration of semiconductor memory devices. However, the high-density integration inevitably reduces the capacitor chip area that stores information (electric charge). The reduction of the electric charge stored in the capacitors causes software errors such that the memory contents of the capacitors might be erroneously read, or destroyed by alpha rays and the like.
To achieve the high-density integration of semiconductor memory devices while maintaining the large capacitance of the storage capacitors, various techniques including a so-called trench capacitor cell configuration have been disclosed.
A conventional trench capacitor cell configuration will be described with reference to FIGS. 7a through 7c, showing a plan view and cross-sectional views, respectively. In FIGS. 7a through 7c, a trench 102 is formed on the surface of a silicon substrate 101. A capacitor is formed along the sidewalls of the trench 102. Thus, the capacitor area can be increased without an increase in chip area. Each of the memory cells comprises a MOSFET and a MOS capacitor.
In this configuration, a field oxide film 103, which isolates respective element regions, is formed on the surface of a p-type silicon substrate. Each of the MOSFETs is formed in an element region isolated by the field oxide film 103. The MOSFET is constituted by source and drain regions 110 and 114 of n-type layers, and a gate electrode 109 formed therebetween through a gate insulating film 108. A storage node electrode 104 is formed on the inner wall of the trench 102 interposing a thermal oxide film 100 therebetween. A capacitor insulating film 105 is formed on the surface of the storage node electrode 104. Further, a plate electrode 106 is buried in the trench 102. The storage node electrode 104, the capacitor insulating film 105 and the plate electrode 106 constitute the MOS capacitor. A word line 109 is formed on the plate electrode 106 through an interlayer insulating film 107.
As described above, the trench capacitor cell configuration utilizing the inner walls of the trench capacitor can be increased up to several times that of the planar configuration. As a result, the chip area for memory cell can be reduced without a decrease in the amount of electric charge to be stored.
However, in the above-described conventional configuration, an undesirable short-circuit layer 200 might be formed in a region from the end portion of the plate electrode 106 to the substrate surface, as shown in FIG. 7c. The short-circuit layer 200 is composed of residual material which should have been removed while the word line 109 was formed by use of an anisotropic etching technique. The short-circuit layer 200 inevitably short-circuits between the gate electrode 109 which serves as the word line (not shown in FIG. 7C) and the adjoining word line 109'. The short-circuit layer 200 is left unetched because of the following reasons. Specifically, a conductive layer (dotted line), which is to be etched, has regions of different thicknesses indicated by arrows t1 and t2 with respect to the etching direction, i.e., the vertical direction, as shown in FIG. 7C. Thus, when the word line 109 is formed by the use of the anisotropic etching technique, the region of arrow t1, which corresponds to the flat portion of the plate electrode 106, can be completely removed. However, if the etching ends on the completion of removing the region of arrow t1, the region of arrow t2, which corresponds to the inclined end portion of the plate electrode 106, cannot be completely removed. The residual material forms the short-circuit layer 100. It is possible to completely remove the region of arrow t2, when the word line 109 is formed by use of the anisotropic etching technique. However, this causes the word line 109 to be excessively etched, and thereby a prescribed thickness thereof cannot be maintained. As a result, the resistance of the word line 109 inevitably increases, and causes a decrease in operations. Further, the thinned word line 109 is easily broken.
More specifically, the cause of the occurrence of the short-circuit layer 200 will be described with reference to FIG. 8, which is a schematic illustration. In FIG. 8, the plate electrode 106 is formed on the field oxide film 103 having a substantially flat surface of uniform thickness. The plate electrode 106 comprises a flat portion 106a and an inclined portion 106b having an inclination angle .theta.. The bottom portion of the inclined portion 106b is defined as an inclined portion's bottom length, and is represented by G (hereinafter simply referred to as bottom length G). As shown in FIG. 7C, the occurrence of the short-circuit layer 200 is caused by the difference between etching lengths of arrows t1 and t2 with respect to the flat portion 106a and the inclined portion 106b shown in FIG. 8. Assume that the bottom length G is designed to be greater and thereby the inclination angle .theta. of the inclined portion 106b becomes smaller. This reduces the difference between etching lengths of arrows t1 and t2. As a result, the occurrence of the short-circuit layer 200 can be avoided. However, in order to meet the recent requirements of the miniaturization and higher-density of elements, the bottom length G must be as small as possible. Thus, the inclination angle .theta. inevitably becomes greater, and thereby the difference between the etching lengths of arrows t1 and t2 also increases.